PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 853726
Date 8/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 3 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules For Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout 5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines 5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines 5.6. DisplayPort Connectors 5.7. HDMI Connectors
5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines x
5.4.1. Channel Recommendations 5.4.2. General Guidelines for PCIe* 3.0 Interface 5.4.3. PCIe* Add-In Card Edge Finger
5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines x
5.5.1. Channel Recommendations 5.5.2. General Guidelines for Ethernet Interface 5.5.3. Quad Small Form-factor Pluggable and Small Form-factor Pluggable Connector Routing
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR4 Interface Design Guidelines 6.4. LPDDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR4 Interface Design Guidelines x
6.3.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.3.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
8. True Differential I/O Interface PCB Routing Guidelines x
8.1. True Differential I/O Specifications
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 3 Device Family PDN Design Summary
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 3 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 3 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 3 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)

The MIPI channel design must meet the MIPI standard board electrical specification. In the MIPI design, board traces, vias, connectors, and cables are part of the board specification, while silicon and package are excluded.

Figure 36. Standard Reference Channel Example to Support up to 2.5 GbpsThis figure shows the supported standard reference channel up to 2.5 Gbps with respect to the maximum board trace length.

To conform to the MIPI standard electrical specification on a MIPI interface, follow these guidelines:

  • The recommended signal trace impedance on board is 100-ohm differential. If the differential channel is also used for LP single-ended signal, Altera recommends that you apply loosely coupled differential transmission lines.
  • To improve the performance after channel simulation, consider backdrilling to minimize the impact of stubs on signal transition vias. Note the increased PCB costs due to this requirement.
  • Control skew matching within ±40 mil between data to clock signals.
  • Keep 3H spacing between pairs and 5H within the pair, where 'H' is the distance from the signal layer to the closest reference layer.
  • Avoid routing noisy signals such as CLK signals or VR modules near MIPI signals.
  • Avoid having MIPI signals reference a noisy power plane.
  • Use use ground isolation with 3H spacing along the global trace at microstrip layer only, when the signal adjacent to MIPI is a high-speed single-ended I/O (≥200 MHz).

The supported MIPI data rate varies based on two different MIPI board trace settings (length):

  • Long reference channel on PCB is supported up to 2.5 Gbps
  • Short reference channel Standard reference channel are supported

Estimate the maximum PCB routing length to conform to the loss requirement.

Table 7.  Supported MIPI Data Rate and Board Electrical Specifications
Data Rate 2.5 Gbps
Supported Reference Channel Long
Insertion Loss Frequency at 1.25 GHz -6.3 dB ±0.5 dB
Insertion Loss Frequency at 5 GHz -20 dB ±0.8 dB
Table 8.  MIPI 2.5 Gbps Board Electrical SpecificationsDetailed requirements for MIPI 2.5 Gbps.
Board Electrical Spec Magnitude Frequency Range
Board Inter-Lane Common Mode Cross Coupling (dB)

< -40 dB

< 16.26×F-40.325

< 12.8×F-36

0 < F ≤ 20 MHz

20 MHz < F ≤ 1.25 GHz

1.25 GHz < F ≤ 1.875 GHz
Differential Return Loss (dB) < -12 dB 0 < F ≤ 1.875 GHz
Board Inter-Lane Differential Cross Coupling (dB)

< -40 dB

< 7.54×F-40.138

0 < F ≤ 20 MHz

20 MHz < F ≤ 1.875 GHz
Board Intra-Lane Cross Coupling < -20 dB 0 < F ≤ 200 MHz
Differential to common-mode conversion and vise versa < -26 dB 0 < F ≤ 1.875 GHz
Note: Altera recommends following the comprehensive TLIS specification in MIPI DPHY V2.1.
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