PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

5.4.1. Channel Recommendations

  • Evaluate the maximum and minimum routing lengths based on specific stack-up and standards.
  • Follow the pair-to-pair stripline spacing rules, where 'H' is referenced to the thinner dielectric side:
    • 5× H for transmitter–to–transmitter and receiver–to-–receiver.
    • 9× H for transmitter–to–receiver.
  • For microstrip routing, use a larger spacing such as 6× H for receiver-to-receiver on Agilex™ 5 system-on-module (SoM) board.
  • Keep total insertion loss and skew within the PCIe* 3.0 specifications.
  • Place the AC coupling capacitors on the FPGA transmitter paths close to the FPGA or connector. Do not place the AC coupling capacitors in the middle of the trace routing. Run a simulation to optimize the cut-out size of AC capacitors, as described in the related information.
Informative:
  • Target differential impedance—85 Ω
  • Differential return loss—better than –15 dB from 0 GHz to 8 GHz