1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 3 Device Family PDN Design Summary
5.4.1. Channel Recommendations
- Evaluate the maximum and minimum routing lengths based on specific stack-up and standards.
- Follow the pair-to-pair stripline spacing rules, where 'H' is referenced to the thinner dielectric side:
- 5× H for transmitter–to–transmitter and receiver–to-–receiver.
- 9× H for transmitter–to–receiver.
- For microstrip routing, use a larger spacing such as 6× H for receiver-to-receiver on Agilex™ 5 system-on-module (SoM) board.
- Keep total insertion loss and skew within the PCIe* 3.0 specifications.
- Place the AC coupling capacitors on the FPGA transmitter paths close to the FPGA or connector. Do not place the AC coupling capacitors in the middle of the trace routing. Run a simulation to optimize the cut-out size of AC capacitors, as described in the related information.
Informative:
- Target differential impedance—85 Ω
- Differential return loss—better than –15 dB from 0 GHz to 8 GHz
Related Information