1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview
9.2. Power Delivery Overview
9.3. Board Power Delivery Network Recommendations
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
9.5. PCB PDN Design Guideline for Unused GTS Transceiver
9.6. PCB Voltage Regulator Recommendation for PCB Power Rails
9.7. Board PDN Simulations
9.8. Agilex™ 3 Device Family PDN Design Summary
5.6. DisplayPort Connectors
Agilex™ 3 devices support DisplayPort (DP) 1.4 up to 8.1 Gbps.
- To minimize return loss, Altera recommends the following:
- Use differential traces for DP signal routing.
- Create a rectangular cut-out under the connector pin on Layer 2. You can optimize the sizes through 3D simulation; or refer to the connector vendor for recommendations.
- Remove the solder mask over the top of the connector pad.
- Maintain an interlane skew of ±250 mils for different DP lanes.
Figure 25. Example of Cut Out Size on Layer 2 of Carrier BoardThis figure shows an example from an Agilex™ 5 carrier board. In the uncoupled region, the trace width follows the single-ended trace width.