PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

5.6. DisplayPort Connectors

Agilex™ 3 devices support DisplayPort (DP) 1.4 up to 8.1 Gbps.
  • To minimize return loss, Altera recommends the following:
    • Use differential traces for DP signal routing.
    • Create a rectangular cut-out under the connector pin on Layer 2. You can optimize the sizes through 3D simulation; or refer to the connector vendor for recommendations.
  • Remove the solder mask over the top of the connector pad.
  • Maintain an interlane skew of ±250 mils for different DP lanes.
Figure 25.  Example of Cut Out Size on Layer 2 of Carrier BoardThis figure shows an example from an Agilex™ 5 carrier board. In the uncoupled region, the trace width follows the single-ended trace width.