PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

3.3. Layer Assignment

  • For high-speed differential traces, avoid long via coupling between the closest transmit (TX) and receive (RX) channels.
  • Make sure the via coupling length is as short as possible to reduce crosstalk.