PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

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ID 853726
Date 8/20/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. BGA Footprint and Land Pattern 3. General PCB Design Considerations 4. VPBGA PCB Routing Guidelines 5. MBGA PCB Routing Guidelines 6. EMIF PCB Routing Guidelines (VPBGA and MBGA) 7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA) 8. True Differential I/O Interface PCB Routing Guidelines 9. Power Distribution Network Design Guidelines 10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs
1. Overview x
1.1. Agilex™ 3 FPGAs and SoCs Packages
2. BGA Footprint and Land Pattern x
2.1. Metal-Defined Board Pad 2.2. Spoked Pad 2.3. Wide Trace Metal-Defined Pad 2.4. Solder Mask-Defined Pad 2.5. Recommended Land Patterns
3. General PCB Design Considerations x
3.1. Impedance Tolerances 3.2. Reference Planes 3.3. Layer Assignment 3.4. Via Drill Size 3.5. Fiber Weave 3.6. PCB Traces 3.7. PCB Vias 3.8. AC Coupling Capacitors 3.9. Other Considerations
3.6. PCB Traces x
3.6.1. Zig-Zag Routing 3.6.2. Image Rotation
4. VPBGA PCB Routing Guidelines x
4.1. Pin Distribution and Ball Pitches 4.2. Fan-Out and Routing Strategy 4.3. Power Pins
5. MBGA PCB Routing Guidelines x
5.1. Typical Design Rules For Type-IV HDI in a 0.5 mm MBGA 5.2. HSSI Breakout 5.3. EMIF Breakout 5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines 5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines 5.6. DisplayPort Connectors 5.7. HDMI Connectors
5.4. GTS Transceiver PCIe* 3.0 Interface Design Guidelines x
5.4.1. Channel Recommendations 5.4.2. General Guidelines for PCIe* 3.0 Interface 5.4.3. PCIe* Add-In Card Edge Finger
5.5. GTS Transceiver Ethernet 10G NRZ Interface Design Guidelines x
5.5.1. Channel Recommendations 5.5.2. General Guidelines for Ethernet Interface 5.5.3. Quad Small Form-factor Pluggable and Small Form-factor Pluggable Connector Routing
6. EMIF PCB Routing Guidelines (VPBGA and MBGA) x
6.1. General DDR Signal Routing Guideline on PCB 6.2. General Notes for EMIF Routing Guidelines Table 6.3. LPDDR4 Interface Design Guidelines 6.4. LPDDR4 Simulation Strategy
6.1. General DDR Signal Routing Guideline on PCB x
6.1.1. FPGA DDR Break Out Routing 6.1.2. DRAM Break Out in Layout Routing 6.1.3. Ground Plane and Return Path
6.3. LPDDR4 Interface Design Guidelines x
6.3.1. LPDDR4 Memory Down Topology (Up to 32-bits Interface) 6.3.2. Tables for Comprehensive Routing Guidelines for Each LPDDR4 Signal
8. True Differential I/O Interface PCB Routing Guidelines x
8.1. True Differential I/O Specifications
9. Power Distribution Network Design Guidelines x
9.1. Agilex™ 3 Power Distribution Network Design Guidelines Overview 9.2. Power Delivery Overview 9.3. Board Power Delivery Network Recommendations 9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 9.5. PCB PDN Design Guideline for Unused GTS Transceiver 9.6. PCB Voltage Regulator Recommendation for PCB Power Rails 9.7. Board PDN Simulations 9.8. Agilex™ 3 Device Family PDN Design Summary
9.2. Power Delivery Overview x
9.2.1. Power Architecture 9.2.2. Rail Merger Requirements 9.2.3. Power Rails Specification 9.2.4. Decoupling Capacitors Recommendation
9.2.1. Power Architecture x
9.2.1.1. Power Budget 9.2.1.2. Power Tree
9.2.3. Power Rails Specification x
9.2.3.1. Power Nets 9.2.3.2. Power Rails Tolerance 9.2.3.3. Power Nets and Transient Specifications
9.2.3.1. Power Nets x
9.2.3.1.1. Agilex™ 3 Package Power Nets and Subsystems Details
9.2.4. Decoupling Capacitors Recommendation x
9.2.4.1. Agilex™ 3 FPGA Packages Board-Level Decoupling Capacitors Summary 9.2.4.2. Agilex™ 3 GTS Transceiver Board-Level Decoupling Capacitors Summary
9.3. Board Power Delivery Network Recommendations x
9.3.1. Board Decoupling Capacitors Guide 9.3.2. FPGA Core Fabric VCC Voltage Regulator Selection 9.3.3. Remote Sense Connections 9.3.4. Load Line Requirements 9.3.5. VCC Core Board Current Slew Rate
9.4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
9.4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation Under Noisy Voltage Regulator
9.5. PCB PDN Design Guideline for Unused GTS Transceiver x
9.5.1. PDN Design Guideline for Unused GTS Transceiver
1. Overview
2. BGA Footprint and Land Pattern
3. General PCB Design Considerations
4. VPBGA PCB Routing Guidelines
5. MBGA PCB Routing Guidelines
6. EMIF PCB Routing Guidelines (VPBGA and MBGA)
7. MIPI Interface Layout Design Guidelines (VPBGA and MBGA)
8. True Differential I/O Interface PCB Routing Guidelines
9. Power Distribution Network Design Guidelines
10. Document Revision History for the PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

9.2.3.1.1. Agilex™ 3 Package Power Nets and Subsystems Details

Table 10.   Agilex™ 3 C-Series FPGA Package Power Rail Nets and Subsystem Details
System Power and Thermal Calculator (PTC) Rail Name Board Connection System Connection
FPGA VCC

VCCL 0.78 V/0.75 V

 VCC supplies power to the Core.
FPGA/PIO VCCP VCCP supplies power to the Periphery.
FPGA/HPS VCCL_HPS VCCL_HPS suppliers’ power to the HPS DSU and periphery circuitry.
FPGA/HPS VCCPLLDIG1_HPS VCCPLLDIG1_HPS: Digital power supply of the main HPS PLLs.
VCCPLLDIG2_HPS VCCPLLDIG2_HPS: Digital power supply of the peripheral HPS PLLs.
FPGA/HPS VCCL_HPS_CORE0_CORE1 Supply power to HPS A55 Core0 and Core1.
FPGA/HPS VCCL_HPS_CORE2 Supply power to HPS A76 Core2.
FPGA/HPS VCCL_HPS_CORE3 Supply power to HPS A76 Core3.
FPGA/SDM VCC_IO_SDM SDM block I/O digital supply voltage sense.
FPGA/SDM VCCL_ADC_SDM HPS DSU and periphery voltage sense.
FPGA/SDM VCCL_SDM

SDM power supply.
FPGA/SDM VCCPLLDIG_SDM

SDM block PLL power pins.
FPGA/SDM VCCH_SDM P1V0_GR1

Voltage rail sense.

You must connect this sense to the VCCERT_GTS (1.0 V) rail for the Agilex™ 3 device with transceiver and connect this sense to VCCL_SDM for the device without transceiver.
FPGA VCCPT P1V8_GR2a Power supply for the IOPLL, programmable power technology, and I/O pre-drivers.
FPGA/HVIO VCCPT_HVIO Pre-driver analog power supply pin for HVIO.
FPGA/SDM VCCIO_SDM Configuration pins power supply.
FPGA/HPS VCCIO_HPS The HPS dedicated I/Os support 1.8 V voltage level.
FPGA/SDM VCCFUSEWR_SDM The required power supply to program (write) the optional, one-time programmable eFuses. The eFuses are integral to the Agilex™ security architecture.
FPGA/HPS VCCPLL1_HPS VCCPLL1_HPS—Supply analog power to the main HPS PLLs.
VCCPLL2_HPS VCCPLL2_HPS—Supply analog power to the peripheral HPS PLLs.
FPGA/SDM VCCADC ADC power pin for the voltage sensors.
FPGA/SDM VCCPLL_SDM VCCPLL_SDM supplies analog power to the SDM block PLLs.
FPGA/PIO VCCIO_PIO_T/B P1V2_GR2b Power supply voltage pins for the I/O banks.
FPGA/SDM VCCIO_PIO_SDM VCCIO_PIO voltage rail sense line.
FPGA VCCRCORE

Power supply for programmable power technology.
FPGA/HVIO VCCIO_HVIO P3V3/2V5/1V8_GR2b Buffer analog power supply pin for HVIO.
FPGA/SDM VCCBAT VCCBAT Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.
Table 11.   Agilex™ 3 GTS Transceiver Power Rail Nets and Subsystem Details
Power and Thermal Calculator (PTC) Rail Name Board Connection System Connection
VCC_HSSI VCCL 0.78 V/0.75 V

GTS transceiver digital logic power supply.

For the devices with speed grade –6S, it is 0.78 V.

For the devices with speed grade –7S, it is 0.75 V.

For more information about the supported pins, refer to the device pin-out file.
VCCERT_GTS P1V0_GR1

GTS transceiver analog 1.0 V logic power pins.

For more information about the supported pins, refer to the device pin-out file.
VCCEHT_GTS P1V8_GR2a

GTS transceiver high-voltage analog power supply pins.

For more information about the supported pins, refer to the device pin-out file.
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