4.2. Fan-Out and Routing Strategy
To facilitate easy routing, the 0.65 mm ball pitch is optimized to have one signal trace routing through on the top layer, as shown in the following figure. Typically, these pins are used as EMIF DQ group and other GPIOs.
In the following figure, the GPIO pins are located at the inner area of the BGA. Every two columns of the GPIOs are spaced approximately 1.45 mm apart. Depending on the specific stack-up design, this spacing allows a fan-out of up to five or six single-ended signals.
To reduce the total layer count, fan out more signals on each layer. Consider implementing vias with 8 mil or 10 mil drill hole size for GPIO pins. For detailed recommendations for EMIF signals with microstrip or stripline routing, including spacing, length matching, maximum routing length, and others, refer to the related information.