PCB Design Guidelines: Agilex™ 3 FPGAs and SoCs

ID 853726
Date 8/20/2025
Public
Document Table of Contents

4.2. Fan-Out and Routing Strategy

Altera recommends the dog-bone fan out structure for Agilex™ 3 VPBGA devices
Figure 15. Dog-Bone Fan-Out Structure


To facilitate easy routing, the 0.65 mm ball pitch is optimized to have one signal trace routing through on the top layer, as shown in the following figure. Typically, these pins are used as EMIF DQ group and other GPIOs.

Figure 16. Example Fan-Out for Two Outermost Rows or Columns of the GPIO Area in the Top LayerThis figure shows fan-out and routing strategy for Agilex™ 3 VPBGA devices.


In the following figure, the GPIO pins are located at the inner area of the BGA. Every two columns of the GPIOs are spaced approximately 1.45 mm apart. Depending on the specific stack-up design, this spacing allows a fan-out of up to five or six single-ended signals.

Figure 17. Example Fan-Out of Inner Layer GPIO Pins, Including EMIFThis figure shows fan-out and routing strategy for Agilex™ 3 VPBGA devices.


To reduce the total layer count, fan out more signals on each layer. Consider implementing vias with 8 mil or 10 mil drill hole size for GPIO pins. For detailed recommendations for EMIF signals with microstrip or stripline routing, including spacing, length matching, maximum routing length, and others, refer to the related information.