F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.3. Unsupported PMA/FEC Modes

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP does not support the following PMA/FEC modes:
  • No support for TX simplex and RX simplex mode for FHT and FEC direct mode.
  • Gearbox feature is disabled for PMA Direct mode.
  • No support for mixtures of PMA modulation modes within the same PMA . That is, a TX-only and RX-only channel cannot be a mixture of NRZ and PAM4 modulation modes.
  • Does not support the reset controller function directly. Rather, reset ports that you expose by means of this IP core route to the tile-wide soft reset controller (SRC).
  • Parameter editor does not support analog parameter settings, such as termination, coupling, or transmitter PMA equalizer parameters. Rather, you must configure analog pin settings, such as termination and coupling, by use of .qsf assignments. This method allows you to reuse the same IP instance for different applications, with various pin analog settings, in different .qsf files.
  • No support for enabling a rate-matching soft FIFO between the user FPGA core logic and the IP for pacing the data valid signal inside the IP.