F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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2.2.8. Bonding Placement Rules

When multiple streams are bonded together, there are pre-defined, allowed locations for EMIBs and lanes based on fracture type and location.

Streams and lanes are placed contiguously in sequence. The primary stream is placed at the highest EMIB number. The secondary stream is placed at the second highest EMIB number. Subsequent streams are likewise placed in descending order.

In the following figures, st_x6 and st_x12 bonding placements can only be used in PMA Direct mode. These placements are primarily meant for a protocol such as JESD204B/C or protocols which require PMA Direct bonding of something other than two, four, eight, or 16 lanes.
Note: When bonding 8 PMA lanes, you must place them within two quads. When bonding 4 PMA lanes, you must place them within one quad.
Figure 35. 400G Primary Stream Placement
If you use eight bonded TX PMA lanes in 400G hard IP with eight streams of a st_x8 fracture:
  • The eight 25 Gbps PMA lanes are denoted as tx_serial_data[7:0].
  • The allowed locations for primary stream tx_serial_data[0] are EMIB_23 and EMIB_15.
  • If EMIB_15 is selected, tx_serial_data[0] is assigned to FGT3_Quad1. Subsequently, tx_serial_data[1] is assigned to EMIB_14 and FGT2_Quad1; tx_serial_data[2] is assigned to EMIB_13 and FGT1_Quad1, with subsequent streams following the same pattern.
Figure 36. 200G Primary Stream Placement
If you use one RX PMA lane in 200G hard IP with two streams of a st_x2 fracture:
  • The 50 Gbps PMA lane is denoted as rx_serial_data[0].
  • The allowed locations for primary stream rx_serial_data[0] are EMIB_7 and EMIB_5.
  • If EMIB_7 is selected, rx_serial_data[0] is assigned to FGT3_Quad1, and the secondary stream is assigned to EMIB_6 and FGT2_Quad1.

The primary lane and stream must be active before and after dynamic reconfiguration. For example, if you require an Ethernet interface that supports dynamic reconfiguration between 200G-CR4 and 100G-CR2 in 400G hard IP:

  • The primary lane is denoted as eth_tx_serial_data[0] and eth_rx_serial_data[0].
  • Both st_x8 and st_x4 fractures are used (the former for 200G-CR4 and the latter for 100G-CR2), but not at the same time.
  • EMIB_23 and EMIB_15 are allowed locations for the st_x8 fracture primary stream.
  • EMIB_23, EMIB_19, EMIB_15 and EMIB_11 are allowed locations for the st_x4 fracture primary stream.
  • Therefore, you can choose either EMIB_23 or EMIB_15 as the primary stream location because they are the allowed locations for both fracture types.

Use the F-Tile Channel Placement Tool for your channel placement planning. Use the Intel® Quartus® Prime Tile Interface Planner to sign off on the channel placement for your board layout.