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Ixiasoft
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Ixiasoft
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
The following chapters describe implementation of the Intel® Agilex™ F-tile physical (PHY) layer IP, PLLs, and clock networks. Refer to these chapters for implementation details of IP instantiation, connection, simulation, and tile placement for Intel® Agilex™ F-tile designs.
Implementation of F-tile PMA/FEC PHY designs involves instantiation and connection of the following required and optional Intel® FPGA IP that is available in the Intel® Quartus® Prime IP catalog:
- F-Tile PMA/FEC Direct PHY Intel® FPGA IP (Required)
- F-Tile Reference and System PLL Clocks Intel® FPGA IP (Required)
- F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP (Optional)18
- Implementing the F-Tile PMA/FEC Direct PHY Intel FPGA IP—describes function, parameters, and ports, bit mapping, core clocking, reset, and bonding of the IP.
- Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP—describes the function, parameters, and ports of the IP.
- Implementing the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP—describes the function, parameters, and ports of the IP.
- F-tile PMA/FEC Direct PHY Design Implementation—describes instantiation, connection, simulation, and tile interface planning using an example design.
Section Content
F-Tile PMA/FEC Direct PHY Intel FPGA IP Overview
Designing with F-Tile PMA/FEC Direct PHY Intel FPGA IP
Configuring the IP
Signal and Port Reference
Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
Clocking
Custom Cadence Generation Ports and Logic
Asserting Reset
Bonding Implementation
Independent Port Configurations
Configuration Registers
Configurable Intel Quartus Prime Software Settings
Configuring the F-Tile PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
Hardware Configuration Using the Avalon Memory-Mapped Interface
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