F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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Document Table of Contents FGT PMA Lane Addressing Example 1

This example demonstrates how to access 16 FGT PMA lane registers within the same F-Tile PMA/FEC Direct PHY Intel® FPGA IP instance.
In this example you place the 16 FGT PMA channels as shown:
  • Instance 1: 16 FGT PMA lanes placed contiguously in one F-tile.
To access the contiguous lanes using the PMA Avalon® memory-mapped interface, you define and control the PMA Avalon® memory-mapped interface's address bits (reconfig_xcvr_addr[21:18]) as shown in the following table. The offset address shown are for the FGT TX equalizer settings.
Table 84.  16 FGT PMA Lanes Design with PMA Avalon® Memory-Mapped Port Indexing
Quad Lane Logical PMA Avalon® Memory-Mapped Port Index [3:0] Offset Address
0 0 0x0 0x47830
1 0x1 0x4F830
2 0x2 0x57830
3 0x3 0x5F830
1 0 0x4 0x47830
1 0x5 0x4F830
2 0x6 0x57830
3 0x7 0x5F830
2 0 0x8 0x47830
1 0x9 0x4F830
2 0xA 0x57830
3 0xB 0x5F830
3 0 0xC 0x47830
1 0xD 0x4F830
2 0xE 0x57830
3 0xF 0x5F830
The F-Tile PMA/FEC Direct PHY Intel® FPGA IP has 16 FGT PMA lanes, the additional MSB address bits [3:0] that represent the Avalon® memory-mapped port index value are 0x0 to 0xF.
For example, you write to the following address to access the registers in that lane:
  • To access quad 0, lane 1, write to 0x14F830
  • To access quad 1, lane 3, write to 0x75F830
  • To access quad 3, lane 2, write to 0xE57830
In this example, each PMA lane has its own Avalon® port memory-mapped port to access the register of the lane.