F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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Document Table of Contents Run-time Reset Sequence Approximate Time Durations

The following table provides approximate times for Run-time Reset Sequence—TX + RX. The numbers are provided for general guidance. They are meant to give an idea of the timescale involved for the reset sequence and are subject to change without notice.

Event Sequence Simulation Max Time Hardware Max Time
tx_reset_ack deassert to tx_ready assert 740 us 60ms
tx_reset assert to tx_ready deassert 400 us 40ms
tx_reset assert to tx_reset_ack assert 600 us 60ms
rx_reset_ack deassert to rx_ready assert 900 us 70ms
rx_reset assert to rx_ready deassert 400 us 40ms
rx_reset assert to rx_reset_ack assert 1.4 ms 190ms