F-tile Architecture and PMA and FEC Direct PHY IP User Guide
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Ixiasoft
6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
- Specify the target device family, click Assignments > Device, and then select Agilex AGIB027R29A2E2V.
- If IP catalog is not already open, click View > IP Catalog in the Intel® Quartus® Prime software.
- In the IP Catalog search field, type f-tile pma, and double-click the F-Tile PMA/FEC Direct PHY Intel® FPGA IP .
Figure 98. F-Tile PMA/FEC Direct PHY Intel® FPGA IP in IP Catalog
- In the parameter editor, specify optional values to configure the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for your protocol implementation:
You can optionally specify the FGT_NRZ_50G_2_PMA_Lanes_Custom_Cadence_ED in the collection of Presets to apply those default parameter values. During parameterization, instantiate the PMA direct channel. The available parameter editor options reflect your channel requirements.
- When parameterization is complete, click the Generate HDL button in the parameter editor to generate the IP instance and supporting files. Under Simulation, select Verilog and either VCS* or ModelSim* for Create simulation model.40
Figure 99. Simulation Options
- Click the Generate button. Your IP variation RTL and supporting files generate according to your specifications, and are added to your Intel® Quartus® Prime project.
The top-level file that generates with the IP instance includes all the available ports for your configuration. Use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP cores in your design, as Connecting the F-tile PMA/FEC Direct PHY Design IP describes.
Section Content
Setting General and Common Datapath Options
Setting TX Datapath Options
Setting RX Datapath Options