F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. Configuring the IP

Use the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in the Intel® Quartus® Prime Pro Edition software to configure the PMA PHY for your protocol implementation.

To instantiate the IP, follow these steps:

  1. To specify the target device family, click Assignments > Device, and then select an Intel® Agilex™ F-tile device, such as AGIB027R29A2E2V.
  2. Click Tools > IP Catalog, type pma in the search field, and select F-Tile PMA/FEC Direct PHY Intel® FPGA IP (under Interface Protocol). The IP parameter editor opens.
  3. In the parameter editor, specify the parameters to customize the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for your protocol implementation. Select one of the following PMA usage modes. The parameter editor guides your parameter value selections.
    • PMA Direct Mode for FGT and FHT
    • FEC Direct mode for FGT and FHT
  4. When parameterization is complete, click the Generate button, and then click the Generate HDL button. Your IP variation RTL and supporting files generate according to your specifications, and are added to your Intel® Quartus® Prime project.

The top-level file generated with the IP instance includes all the available ports for your configuration. Use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP cores in your design, such as the F-Tile Reference and System PLL Clocks Intel® FPGA IP, TX and RX serial data pins, and the data generator and data checker IP.

The F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports only the following simulators for this release:

  • VCS*
  • ModelSim* SE
  • QuestaSim*
  • Xcelium*