F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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Document Table of Contents

3.8.1. Reset Signal Requirements

The following requirements apply to reset signal use for F-tile PMA/FEC Direct PHY designs:
  • Ensure that tx_reset/rx_reset remain asserted until tx_reset_ack/rx_reset_ack goes high.
  • Expect random data if tx_ready/rx_ready is not asserted.
  • In forward error correction (FEC) modes, during reset sequencing, after tx_am_gen_start is asserted, start sending alignment markers and assert tx_am_gen_2x_ack after two alignment markers are sent. tx_am_gen_start goes high as part of reset sequence (that is, before tx_ready is asserted).
  • In FEC modes when sending alignment markers, you can pace tx data valid with the tx_cadence signal.
  • For duplex configurations, you can assert tx_reset and rx_reset independently.