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6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
To instantiate a RS-FEC direct design, follow the steps mentioned in section Instantiating the F-Tile Reference and System PLL Clocks Intel FPGA IP. In addition to the PMA data path parameterization, a RS-FEC direct design allows you to enable the RS-FEC mode for forward error correction in a NRZ or PAM4 design configuration.
The RS-FEC option in F-Tile PMA/FEC Direct PHY Intel® FPGA IP supports the RS-FEC modes specified in section FEC Architecture. Also refer to F-Tile Supported FEC Modes and Compliance Specifications for a comprehensive list of RS-FEC modes in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP. Additionally, refer to section FEC Placement Rules for rules to follow when configuring a RS-FEC direct design.
In the RS-FEC tab of the F-Tile PMA/FEC Direct PHY Intel® FPGA IP, you select the Enable RS-FEC to configure a design with FEC as shown in the following figure.
Based on the RS-FEC mode and data rate for your design, you align the PMA parallel clock frequency and choose the System PLL frequency accordingly. Ensure that the System PLL frequency you choose in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP aligns with the F-Tile Reference and System PLL Clocks Intel® FPGA IP reference clock frequency.
There are additional options that you can enable for your RS-FEC design. To enable the loopback select the Enable RS-FEC loopback option. You can also enable the Enable RS-FEC data interleave pattern option. When you enable this option, the RS-FEC lanes are bit-interleaved on each physical lane by 64/80 bits. The default value is Off.
When you enable the RS-FEC feature in your design, the TX and RX deskew logic is enabled. Refer to section Deskew Logic for more information about the deskew logic in the TX and RX datapath.
In a FEC direct design, during reset sequencing, after tx_am_gen_start is asserted, start sending the alignment markers and assert tx_am_gen_2x_ack after two alignment markers are sent. The tx_am_gen_start goes high as part of the reset sequence, before tx_ready is asserted. In addition, in the FEC direct mode, you can pace the TX data valid signal with the tx_cadence signal.
For example, in the 100G FEC direct design, the alignment marker (AM) cycle is 81920 clock cycles and the AM pulse width is 5 clock cycles wide. In addition, the TX data is unscrambled. If a FEC direct design does not lock or align, the RX data is zero.
|FEC Mode||AM Pulse Width (Number of Cycles at IP Interface)|
|128GFC, 200G, 400G||2|
When FEC is configured in 200G or 400G variant modes, you should not scramble or descramble the data as this is done by the RS-FEC hard IP. In all other FEC configurations, such as 25G, 50G or 100G, you have to scramble the input data and you have to descramble output data.
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