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6.7. Simulating the F-Tile PMA/FEC Direct PHY Design
Simulation of the F-tile PMA/FEC Direct PHY design requires running the Intel® Quartus® Prime Compiler's Analysis & Elaboration and Support-Logic Generation stages to elaborate the component IP in your design. Next, you generate the simulator setup scripts for the Synopsys VCS* simulator or ModelSim* simulator. You can modify and use the setup scripts to elaborate and simulate your design and testbench.
The simulation flow for F-tile differs from other serial interface tiles. The difference in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP simulation flow is that you cannot simulate individual IP files.
To simulate the F-tile PMA/FEC Direct PHY design using VCS* :
- Click Processing > Start > Start Analysis & Elaboration. Review and correct any error messages.
- On the Compilation Dashboard, click Support-Logic Generation. Review and correct any error messages.
Note: A <top_level>_auto_tiles.sv file is auto-generated in the support_logic folder. For example, when the top-level entity is top, the generated file is top_auto_tiles.sv. You have to instantiate this in your test bench.
- Click Tools > Generate Simulator Setup Script for IP and retain the default options. Ensure that you do not turn on the Use top-level entity names from Quartus project option.
Figure 110. Generate Simulator Setup Script for IP Dialog Box
- Click OK. The vcs_setup.sh file generates in the synopsys/vcs directory and vcs_files.tcl generates in the common directory.
- Navigate to the /synopsys/vcs directory.
- Review the instructions in vcs_setup.sh to create the vcs_sim.sh file for your simulation. The following shows an example vcs_sim.sh. Your vcs_sim.sh content varies by your design characteristics.
source ./vcs_setup.sh \ TOP_LEVEL_NAME=top_tb \ QSYS_SIMDIR=../.. \ USER_DEFINED_ELAB_OPTIONS="\"-full64 +v2k -hsopt=gates \ +systemverilogext+.sv -sverilog -lca +lint=TFIPC-L +lint=PCWM -wreal res_def \ -xlrm coerce_nettype -timescale=1ns/1ps +vcs+vcdpluson +vpddrivers \ +define+TIMESCALE_EN +define+INTC_FUNCTIONAL +define+RTLSIM \ +define+SSM_SEQUENCE \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SPEC_FORCE \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_SIMULATION \ +define+IP7581SERDES_UXS2T1R1PGD_PIPE_FAST_SIM +error+1000 \ +define+__SRC_TEST__ -debug_access+r+driver+f -debug_region+encrypt \ +rad -f ./filelist.f \" " \ USER_DEFINED_ELAB_OPTIONS_APPEND="\" -l vcs.log\" " ./simv +lic+wait -l simulation.log +fsdb+mda=on +fsdbfile+novas.fsdbNote:
In order to provide a reduction in real-time simulation duration, you can use a Fast Sim model. This model is enabled via a macro in the simulation run scripts. The syntax to enable the Fast Sim model is as follows:
- Create your test bench. When calling the top level module in the test bench, the module name must be the same as instance name. For example:
A mismatch between the module and instance names causes errors during compilation. For example, the following produces errors during compilation:
top top ( ports passing );
Also be sure to add this instantiation in your test bench:
top top_instant0 ( ports passing );
For example, <any names> can be top_auto_tiles_inst1.
top_auto_tiles <any names> ();
- Create the filelist.f file. vcs_setup.sh contains the instructions for filelist.f. filelist.f contains all your testbench files and top-level. Note that the file location is relative to the vcs_sim.sh command. The following shows one example filelist.f. Your filelist.f content varies, depending on your design characteristics.
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN # # # # Compile all design files and testbench files, including the top level. # # (These are all the files required for simulation other than the files # # compiled by the Quartus-generated IP simulation script) # # # +systemverilogext+.sv # <design and testbench files, compile-time options, elaboration options> # # # # DESIGN FILE LIST & OPTIONS TEMPLATE - END ../../top.v ../../top_tb.v
- Start VCS compilation and simulation.
- Launch waveform viewer.
PAM4 Encoding Schemes in Simulation
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