A newer version of this document is available. Customers should click here to go to the newest version.
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
The F-Tile PMA/FEC Direct PHY Intel® FPGA IP enables access to the PMA Direct and FEC Direct modes via the Intel® Quartus® Prime IP parameter editor.
The PMA Direct mode bypasses the MAC, PCS, and FEC Hard IP block. You can configure the PMA interface, F-tile interface, and core interface FIFOs in the datapath into in various modes, including elastic, phase compensation, and register mode.
The F-Tile PMA/FEC Direct PHY Intel® FPGA IP is for use in proprietary protocol configurations. The IP is not used as a basic building block in other Intel F-tile high-speed protocol IP, such as Ethernet, CPRI, and Interlaken. Rather, each protocol IP has its own configuration of the PMA hard block.
- PMA Direct Mode with PMA Clocking, PMA Direct Mode with PMA Clocking
- PMA Direct Mode with System PLL Clocking, PMA Direct Mode with System PLL Clocking
- FEC Direct Mode with System PLL Clocking and Gearbox Enabled, FEC Direct Mode with System PLL Clocking and Gearbox Enabled
You can use the PMA/FEC Direct PHY Intel FPGA IP to configure the datapath into PMA or FEC direct mode. If you enable the FEC mode, the FEC block is enabled as well. The top-level file that generates with the IP instance includes all the available ports for your configuration. Use these ports to connect the F-Tile PMA/FEC Direct PHY Intel® FPGA IP to other IP cores in your design, such as the F-Tile Reference and System PLL Clocks Intel® FPGA IP, TX and RX serial data pin IP, and the data generator and data checker IP. Refer to the block diagram in F-tile PMA/FEC Direct PHY Design IP Connections.
Did you find the information on this page useful?