F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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Document Table of Contents

5.2. IP Port List

For details on the signals in the following table, refer to the Avalon® Interface Specifications .
Table 100.   F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP Port List
Port Name Direction Width Description
g_avmm_clk Input 1

Global Avalon® memory-mapped interface clock

100-150 MHz

g_avmm_reset Input 1

Global Avalon® memory-mapped interface reset

High active, asynchronous assertion, and synchronous de-assertion. Hold high during power-on

g_avmm_addr Input 18

Word address

Each address has 32 bits; byte selection is done through byte-enable.

g_avmm_byteenable Input 4 Byte enable signal to enable 8 bit access
g_avmm_write Input 1 Write enable
g_avmm_writedata Input 32 32 bit write data
g_avmm_read Input 1 Read enable
g_avmm_readdata Output 32 32 bit read data
g_avmm_waitrequest Output 1 Wait request
g_avmm_readdatavalid Output 1 Data valid signal for read data