F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023

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5.4. Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP

For a design where multiple IP instances are accessed by a single F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP, you need to use the corresponding base address to access the separate IP instances. The base address is determined by the Ethernet mode, and it can be looked up through the fracture type by using the following table. You can use the F-Tile Channel Placement Tool to find out the fracture type of each IP instance.
Table 102.  Fracture Type and Ethernet Mode Mapping
Stream Fracture Type and Ethernet Mode Mapping
Stream0 st_x1_0 (25GE_0) st_x2_0 (50GE_0) st_x4_0 (100GE_0) st_x8_0 (200GE_0) st_x16_0 (400GE_0)
Stream1 st_x1_1 (25GE_1)
Stream2 st_x1_2 (25GE_2) st_x2_1 (50GE_1)
Stream3 st_x1_3 (25GE_3)
Stream4 st_x1_4 (25GE_4) st_x2_2 (50GE_2) st_x4_1 (100GE_1)
Stream5 st_x1_5 (25GE_5)
Stream6 st_x1_6 (25GE_6) st_x2_3 (50GE_3)
Stream7 st_x1_7 (25GE_7)
Stream8 st_x1_8 (25GE_8) st_x2_4 (50GE_4) st_x4_2 (100GE_2) st_x8_1 (200GE_1)
Stream9 st_x1_9 (25GE_9)
Stream10 st_x1_10 (25GE_10) st_x2_5 (50GE_5)
Stream11 st_x1_11 (25GE_11)
Stream12 st_x1_12 (25GE_12) st_x2_6 (50GE_6) st_x4_3 (100GE_3)
Stream13 st_x1_13 (25GE_13)
Stream14 st_x1_14 (25GE_14) st_x2_7 (50GE_7)
Stream15 st_x1_15 (25GE_15)