F-tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 1/25/2023
Public

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Document Table of Contents

10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.01.25 22.4 Updated the FHT Loopback Mode figure with the correct Deserializer block location.
2022.12.19 22.4 Made the following changes:
  • Updated Clock Rules and Restrictions section with additional information about the reference clocks and a new note.
  • Updated FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table; renamed cursor to tap, and updated the footnotes.
  • Added equations based on device OPN list for the transmitter buffer equalizer parameters in the FGT Transmitter Buffer and Phase Generator section.
  • Corrected the preset naming in the F-Tile PMA/FEC Direct PHY Intel FPGA IP Available Parameter Presets table in Preset IP Parameter Settings section.
  • Updated the description for the PMA parallel clock frequency parameter in General and Common Datapath Options table.
  • Updated the Show Preset Settings figure in Example Design Generation section.
  • Corrected tx_coreclkin and rx_coreclkin signal names in Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source section.
  • Corrected the k counter descriptions and equations in FGT PMA Fractional Mode section.
  • Added new information about meeting jitter specifications for OTN/SDI and in other modes in FGT PMA Fractional Mode section.
  • Updated rx_ready signal description in Reset Signal Descriptions table.
  • Updated the steps and figure in the Run-time Reset Sequence—TX section.
  • Updated the steps and figure in the Run-time Reset Sequence—RX section.
  • Updated the steps and figure in the Run-time Reset Sequence—TX + RX section.
  • Updated column header for FHT PMA Lane Number and Offset Address and FGT PMA Lane Number and Offset Address tables in Lane Offset Address section.
  • Updated descriptions for calculating the incremental lane numbers for the FHT PMA and FGT PMA in Lane Offset Address section.
  • Added .qsf settings to bypass RX auto adaptation in Configurable Intel Quartus Prime Software Settings section.
  • Updated Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage with additional information about the system PLL reference clock.
  • Updated Guidelines to Indicate all System PLL Reference Clocks are Ready with additional information about using the internal clock to calibrate and configure the device, information about PCIe specification compliance, and OPN device list that supports Refclk is available at power-on parameter.
  • Added additional information in Example of Reference Clock Availability at Device Programming section to clarify the example.
  • Added tip for step 5b. in Hardware Flow Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP .
  • Added new section Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP with several topics with examples.
  • Updated the FGT transmitter equalizer cursor naming, added additional tool link for various devices based on OPNs, and updated figure in F-Tile TX Equalizer Tool section.
  • Updated the FGT transmitter equalizer cursor naming, updated descriptions for RX Ready and PRBS locked parameters in Transceiver Toolkit Parameter Settings table.
2022.11.03 22.3 Added a clarifying note about the SATA and USB protocol modes in sections: FGT PMA Configuration Rules for SATA and USB mode and TX Parallel Data Mapping Information for SATA and USB Protocol Modes for Different Configurations.
2022.09.26 22.3 Made the following changes:
  • Updated FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table with total slice values for different OPNs.
  • Updated tx_reset_ack and rx_reset_ack signal descriptions in the Reset Signals and Reset Signal Descriptions tables.
  • Added new parameters FGT PMA configuration rules and Enable simplified TX data interface in General and Common Datapath Options table.
  • Added new section FGT PMA Configuration Rules for SATA and USB mode.
  • Added new parameters Enable fgt_tx_beacon port and Enable Spread Spectrum clocking in TX FGT Datapath Parameters table for SATA and USB support.
  • Added new parameters Enable fgt_rx_cdr_fast_freeze_sel port and Enable fgt_rx_cdr_set_locktoref port in RX FGT PMA Parameters table for GPON support.
  • Updated descriptions for Enable fgt_rx_signal_detect port and Enable fgt_rx_signal_detect_lfps port parameters in RX FGT PMA Parameters table for SATA and USB support.
  • Corrected TX PMA Status Signals to TX PMA Control Signals and added new signal fgt_tx_pma_elecidle to the table.
  • Added new section TX Parallel Data Mapping Information for SATA and USB Protocol Modes for Different Configurations.
  • Updated and replaced PMA Avalon® memory-mapped with Global Avalon® memory-mapped interface in Guidelines to Indicate all System PLL Reference Clocks are Ready section and the examples.
  • Added additional examples in step 6. of Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP section.
  • Updated Simulating the F-Tile PMA/FEC Direct PHY Design section with information about the auto-generated file names.
2022.06.24 22.2 Made the following changes:
  • Updated F-Tile Supported FEC Modes and Compliance Specifications table with Fibre Channel 64G support and added note.
  • Clarified fourth bullet in Clock Rules and Restrictions section with updated rules for the FHT microcontroller reference clock.
  • Added new figure for TX termination in FGT Transmitter Buffer and Phase Generator.
  • Added new figure for RX termination in FGT Receiver Buffer and Equalizer.
  • Added new topic Register Map IP-XACT Support in Configuring the IP section.
  • Added instructions to simulate example design using VCS* MX and Xcelium* simulators in Example Design Simulation section.
  • Added note for tx_pll_refclk_link and rx_cdr_refclk_link signals in the TX and RX Reference Clock and Clock Output Interface Signals table.
  • Updated FGT Attribute Access Method section with additional information and tables.
  • Added a new example for serial loopback enable and disable in FGT Attribute Access Method section.
  • Deleted note in step 7. of FGT Attribute Access Method Example 2.
  • Added new parameter Refclk is available at power-on in Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Added new section Guidelines to Indicate all System PLL Reference Clocks are Ready in Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter.
  • Updated step 5. of Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP.
  • Added FEC alignment marker information and table in Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP
  • Added data scrambling and de-scrambling information for FEC in Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP.
  • Updated Running Eye Viewer Tests with an additional step and figures.
  • Added information about Autosweep in Running Link Optimization Tests.
2022.03.28 22.1 Made the following changes:
  • Clarified third bullet in Clock Rules and Restrictions section with updated rules for the system PLL reference clock.
  • Added note about bonding rules in the Bonding Placement Rules section.
  • Added new topic Tuning the Fractional Value in Fractional Mode in the FGT PMA Fractional Mode section.
  • Added PMA Reconfiguration Interface column in the Reset Signals—Block Level table and added a note about the reconfig_xcvr_reset signal usage.
  • Updated TX equalization main tap example setting for FHT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Added FGT Attribute Access Method Example 2 in FGT Attribute Access Method section for TX and RX polarity inversion.
  • Updated Running BER Tests section with information about the Actions sub-menu.
  • Updated Running Eye Viewer Tests section with detailed description about using the Eye Viewer tool for eye height measurement for the FGT PMA.
2021.12.15 21.4 Made the following changes:
  • Updated Increment and Decrement Size column in the FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes table.
  • Added footnote for System PLL frequency description in General and Common Datapath Options table.
  • Added footnote for TX FGT PLL reference clock frequency description in TX FGT Datapath Parameters table.
  • Added footnote to TX and RX Reference Clock and Clock Output Interface Signals table.
  • Removed note for Enable rx_cdr_divclk_link0 port and Enable rx_cdr_divclk_link1 port parameters in the RX FGT PMA Parameters table.
  • Updated Example Design Generation with RS-FEC example design information.
  • Added note to Clocking section in Implementing the F-Tile PMA/FEC Direct PHY Intel FPGA IP chapter.
  • Added RX invert P and N, RX termination, TX invert P and N, TX termination, TX out tristate enable and TX equalization qsf settings for FHT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Removed RX termination mode select qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Added TX equalization qsf setting for FGT PMA in Configurable Intel Quartus Prime Software Settings section.
  • Updated steps 4a, 6, 8a, 10c, 13c, 14b and 14c in the FGT Attribute Access Method Example topic.
  • Reorganized information in the Implementing the F-Tile Reference and System PLL Clocks Intel FPGA IP chapter to make it clearer.
  • Removed note for Enable FGT CDR Output #0 and Enable FGT CDR Output #1 parameters in the F-Tile Reference and System PLL Clocks Intel FPGA IP Parameters table.
  • Added description to specify qsf location assignment for the out_cdrclk_i port in the F-Tile Reference and System PLL Clocks Intel FPGA IP Port List table.
  • Added new section Guidelines for F-Tile Reference and System PLL Clocks Intel FPGA IP Usage.
  • Updated step 5 of the Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP section.
  • Updated F-tile PMA/FEC Direct PHY Design Implementation chapter to remove references to design example.
  • Updated F-Tile Transceiver Toolkit GUI, Collection View Tab of the F-Tile Transceiver Toolkit GUI, Toolkit Explorer, Example BER Test Setup and Results for the FGT PMA figures in the Debugging F-Tile Transceiver Links chapter.
  • Updated PMA naming in the Running BER Tests section.
  • Updated Transceiver Toolkit Parameter Settings table with new information.
  • Updated Creating Transceiver Links section with Import Collections and Export Collections details.
  • Added footnote for TX Equalization Parameters in the Transceiver Toolkit Parameter Settings table.
2021.10.15 21.3 Made the following changes:
  • Updated the Preserving Unused PMA Lanes section.
  • Updated the Number of system copies parameter in General and Common Datapath Options table.
  • Added Enable Core PLL mode parameter in TX FGT Datapath table.
  • Updated Enable FHT RX data profile parameter in RX FHT PMA Parameters table.
  • Updated the Example Design Generation topic in the Configuring the IP section.
  • Updated parameter names to match with GUI names in Avalon® Memory Mapped Interface Parameters table.
  • Added description for Number of system copies parameter in the Signal and Port Reference section.
  • Updated description of the FGT PMA Fractional Mode section.
  • Added new topic Run-time Reset Sequence Approximate Time Duration in Run-time Reset Sequence—TX + RX section.
  • Updated step 4 onwards in the Run-time Reset Sequence—TX with FEC section
  • Updated description of the Lane Offset Address section.
  • Added new topic Logical Avalon Memory-Mapped Port Indexing in Configuration Registers section.
  • Updated steps in FGT Attribute Access Method Example.
  • Added footnote that ETHERNET_FREQ_805_322 is not supported in section Mode of System PLL - System PLL Reference Clock and Output Frequencies.
  • Added new section Hardware Flow Using the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP in Implementing the F-Tile Global Avalon Memory-Mapped Interface Intel FPGA IP chapter.
  • Added the following new sections in the F-tile PMA/FEC Direct PHY Design Example Implementation chapter.
    • Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel FPGA IP.
    • PAM4 Encoding Schemes in Simulation.
    • F-tile Interface Planner Design Example.
    • Updated the Simulating the F-tile PMA/FEC Direct PHY Design Example section.
  • Added and updated the following sections in the Supported Tools chapter.
    • F-Tile PMA and FEC Direct Port Mapping Calculator.
    • F-Tile Clocking and Datapath Tool.
    • F-Tile TX Equalizer Tool.
  • Added new chapter Debugging F-Tile Transceiver Links.
2021.08.18 21.2
  • Added the following new sections and updated table in Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP chapter:
    • Configuration Registers.
    • Configurable Intel® Quartus® Prime Software Settings.
    • Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing.
    • Hardware Configuration Using the Avalon® Memory-Mapped Interface.
    • Added loopback mode in TX FHT PMA Parameters table.
  • Added new topic in F-Tile Placement Rules section in the F-Tile Architecture chapter:
    • Preserving Unused PMA Lanes.
  • Added new chapter Supported Tools.
  • Added new chapter Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide.
    • Consolidated the Document Revision History section of each chapter into this chapter.
2021.07.23 21.2 Updated tx_am_gen_start and tx_am_gen_2x_ack signal directions in the following tables:
  • Reset Signals table.
  • Reset Signal Descriptions table.
2021.06.24 21.2 Initial document release.

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