A newer version of this document is available. Customers should click here to go to the newest version.
1. F-tile Overview 2. F-tile Architecture 3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP 5. Implementing the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP 6. F-tile PMA/FEC Direct PHY Design Implementation 7. Supported Tools 8. Debugging F-Tile Transceiver Links 9. F-tile Architecture and PMA and FEC Direct PHY IP User Guide Archives 10. Document Revision History for F-tile Architecture and PMA and FEC Direct PHY IP User Guide
2.1.1. FHT and FGT PMAs 2.1.2. 400G Hard IP and 200G Hard IP 2.1.3. PMA Data Rates 2.1.4. FEC Architecture 2.1.5. PCIe* Hard IP 2.1.6. Bonding Architecture 2.1.7. Deskew Logic 2.1.8. Embedded Multi-die Interconnect Bridge (EMIB) 2.1.9. IEEE 1588 Precision Time Protocol for Ethernet 2.1.10. Clock Networks 2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping 2.2.2. Determining Which PMA to Map to Which Fracture 2.2.3. Hard IP Placement Rules 2.2.4. IEEE 1588 Precision Time Protocol Placement Rules 2.2.5. Topologies 2.2.6. FEC Placement Rules 2.2.7. Clock Rules and Restrictions 2.2.8. Bonding Placement Rules 2.2.9. Preserving Unused PMA Lanes
184.108.40.206. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT 220.127.116.11. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT 18.104.22.168. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT 22.214.171.124. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT 126.96.36.199. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT 188.8.131.52. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT 184.108.40.206. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 220.127.116.11. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT 18.104.22.168. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT 22.214.171.124. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview 3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP 3.3. Configuring the IP 3.4. Signal and Port Reference 3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath 3.6. Clocking 3.7. Custom Cadence Generation Ports and Logic 3.8. Asserting Reset 3.9. Bonding Implementation 3.10. Independent Port Configurations 3.11. Configuration Registers 3.12. Configurable Intel® Quartus® Prime Software Settings 3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.4.1. TX and RX Parallel and Serial Interface Signals 3.4.2. TX and RX Reference Clock and Clock Output Interface Signals 3.4.3. Reset Signals 3.4.4. RS-FEC Signals 3.4.5. Custom Cadence Control and Status Signals 3.4.6. TX PMA Control Signals 3.4.7. RX PMA Status Signals 3.4.8. TX and RX PMA and Core Interface FIFO Signals 3.4.9. PMA Avalon® Memory Mapped Interface Signals 3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information 3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations 3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1) 3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2) 3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements 3.8.2. Power On Reset Requirements 3.8.3. Reset Signals—Block Level 3.8.4. Reset Signals—Descriptions 3.8.5. Status Signals—Descriptions 3.8.6. Run-time Reset Sequence—TX 3.8.7. Run-time Reset Sequence—RX 3.8.8. Run-time Reset Sequence—TX + RX 3.8.9. Run-time Reset Sequence—TX with FEC
6.1. Implementing the F-tile PMA/FEC Direct PHY Design 6.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP 6.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP 6.5. Enabling Custom Cadence Generation Ports and Logic 6.6. Connecting the F-tile PMA/FEC Direct PHY Design IP 6.7. Simulating the F-Tile PMA/FEC Direct PHY Design 6.8. F-tile Interface Planning
5.4. Examples of Register Access Using the F-Tile Global Avalon® Memory-Mapped Interface Intel® FPGA IP
8.2.4. Creating Transceiver Links
Transceiver links are identified automatically when a receiver and transmitter share the same channel. Each enabled transmitter and receiver channel on all loaded and linked devices is displayed in the Toolkit Explorer as shown in the following figure.
Figure 126. Toolkit Explorer
You can create a custom collection to view and configure TX and RX channels. If you want to create TX and RX paths between different physical channels, whether they are in the same device or in different devices, you must manually create new links. To have TX and RX paths between different physical channels, make sure you have an external loopback either using a loopback cable or card on the board to have physical connections between the channels.
To manually create transceiver links that have TX and RX channels in different physical channel locations, follow these steps:
- Choose the TX and RX pair you want to link.
- Right-click to create a collection and specify a name in the Add to Collection box.
- Click OK. The link you create adds to the Collections box.
- Click Open Toolkit. You can also open all the channels in one view by double-clicking the instances in the Details box. The name of the channels collection is automatically added.
- Go to main Collections pane view where you can control and monitor the channels.
Figure 127. Export CollectionsYou can also load a previously saved collection. Right-click in the Collections window and select Import Collections as shown in the following figure.
Figure 128. Import Collections
Did you find the information on this page useful?