CvP initialization divides the design into periphery and core images. The periphery image is stored in a local flash device on the PCB. You can program the periphery through JTAG. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.
You must specify CvP initialization mode in the Quartus Prime software by selecting the CvP Settings Power up and subsequent core configuration and also turn on Enable Configuration via Protocol
in the Intel® Arria® 10 Hard IP for PCI Express
. You might choose CvP initialization to prevent unauthorized access to the core image as well as save cost by storing the core image in the host memory.
Figure 4. Design Flow for CvP InitializationThe following figure provides the high-level steps for CvP Initialization with periphery image configured through Active Serial configuration mode.
Note: For CvP initialization, you must use the CMU PLL and the Hard Reset Controller for the PCI Express Hard IP.
The CvP initialization demonstration walkthrough includes the following steps:
- Generating the Synthesis HDL Files for Intel Arria 10 PCI Express IP Core
- Setting up the CvP Parameters in Device and Pin Options
- Compiling the Design
- Splitting the SOF File
- Bringing up the Hardware