Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Public
Document Table of Contents

4.3.4. CvP Status Register

Table 10.  CvP Status Register (Byte Offset: 0x21C)
Bits Name Reset Value Access Description
[31:26] 0x00 RO Reserved.
[25] PLD_CORE_READY Variable RO From FPGA fabric. This status bit is provided for debug.
[24] PLD_CLK_IN_USE Variable RO From clock switch module to fabric. This status bit is provided for debug.
[23] CVP_CONFIG_DONE Variable RO Indicates that the FPGA control block has completed the device configuration via CvP and there were no errors.
[22] Variable RO Reserved.
[21] USERMODE Variable RO Indicates if the configurable FPGA fabric is in user mode.
[20] CVP_EN Variable RO Indicates if the FPGA control block has enabled CvP mode.
[19] CVP_CONFIG_ERROR Variable RO Reflects the value of this signal from the FPGA control block, checked by software to determine if there was an error during configuration.
[18] CVP_CONFIG_READY Variable RO Reflects the value of this signal from the FPGA control block, checked by software during programming algorithm.
[17:0] Variable RO Reserved.