1. CvP Initialization in Intel® Arria® 10 2. Design Considerations for CvP Initialization in Intel® Arria® 10 3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 4. CvP Driver and Registers 5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register 4.3.2. Altera-defined Vendor Specific Header Register 4.3.3. Altera Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
5.1. Benefits of Using PR over PCI Express
The PR over PCI Express solution has the following advantages:
- Enables dynamic updates to portions of the FPGA design’s core such as LAB, MLAB, DSP and RAM while the rest of the design continues to run.
- Facilitates hardware acceleration.
- Design protection: PR over PCIe ensures the PCIe host can exclusively access the FPGA fabric image which provides protection against unauthorized design tampering or copying.
- Image update without system down time: Allows a portion of the FPGA fabric to be updated through the PCIe link without a host reboot or FPGA full chip re-initialization.
- Unlike Configuration via Protocol (CvP) which requires the bottom left PCIe Hard IP block be used, any Hard IP for PCI Express IP Core can be used for PR over PCIe. The Hard IP Core must be configured as an Endpoint.
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