Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

5.1. Benefits of Using PR over PCI Express

The PR over PCI Express solution has the following advantages:
  • Enables dynamic updates to portions of the FPGA design’s core such as LAB, MLAB, DSP and RAM while the rest of the design continues to run.
  • Facilitates hardware acceleration.
  • Design protection: PR over PCIe ensures the PCIe host can exclusively access the FPGA fabric image which provides protection against unauthorized design tampering or copying.
  • Image update without system down time: Allows a portion of the FPGA fabric to be updated through the PCIe link without a host reboot or FPGA full chip re-initialization.
  • Unlike Configuration via Protocol (CvP) which requires the bottom left PCIe Hard IP block be used, any Hard IP for PCI Express IP Core can be used for PR over PCIe. The Hard IP Core must be configured as an Endpoint.

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