Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide
ID
683871
Date
9/01/2020
Public
1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
1.5. CvP Compression and Encryption Features
Data Compression
You can choose to compress the core image by turning on the Generate compressed bitstream option in the Configuration page of the Device and Pin Options dialog box in the Quartus Prime software. The periphery image cannot be compressed. Compressing the core image reduces the storage requirement.
Data Encryption
You can choose to encrypt the core image. The periphery image cannot be encrypted. To configure the FPGA with an encrypted core image, you must pre-program the FPGA with a security key. This key is then used to decrypt the incoming configuration bitstream.
A key-programmed FPGA can accept both encrypted and unencrypted bitstreams if you configure the FPGA using the AS, PS, or FPP scheme. However, if you use CvP, a key-programmed FPGA can only accept encrypted bitstreams. Use the same key to encrypt all revisions of the core image.
Key Types | Active Serial | Passive Serial | Fast Passive Parallel | |
---|---|---|---|---|
External Clock | Internal Clock | External Clock | External Clock | |
Volatile key | Yes | Yes | Yes | Yes |
Non-volatile key | No | 12.5 MHz | Yes | Yes |