4.3.5. CvP Mode Control Register
This is the number of clocks to send for every CvP data write. This is also known as CDRATIO (clock to data ratio).
Set this field to one of the values below depending on your configuration image:
|||CVP_FULLCONFIG||1'b0||RW||A value of 1 indicates a request to the control block to reconfigure the entire FPGA including the Hard IP for PCI Express and bring the PCIe link down.|
|||HIP_CLK_SEL||1'b0||RW||Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The following encodings are defined:
|||CVP_MODE||1'b0||RW||Controls whether the Hard IP for PCI Express is in CVP_MODE or normal mode. The following encodings are defined:
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