Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

5.4. Partial Reconfiguration IP Core

PR over PCIe is performed using the PR IP core as an internal host residing in the core logic, which automatically instantiates the corresponding crcblock and prblock WYSIWYG atom primitives.
Figure 13. PR IP Core as an Internal Host
During partial reconfiguration, the PR Control Block (CB) is in Passive Parallel x16 or x32 programming mode.
Figure 14. PR IP Core Components
When you instantiate the PR IP core, the Main Controller module which includes the Control Block Interface Controller, Freeze/Unfreeze Controller, and the Data Source Controller are all instantiated. A Data Source Interface module provides you with a JTAG Debug Interface and PR Data Interface.

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