Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

3.5.4. Modifying MSEL/DIP switch on Intel® Arria® 10 Dev-Kit

The MSEL/DIP switch labeled SW5 on the back of the Intel® Arria® 10 FPGA Development Kit. The right position signifies logic zero and the left position signifies logic one. For example, to set the MSEL [2:0] = 011 follow the sequence as left, left, right from top to bottom.
MSEL Pin Settings for Each Configuration Scheme of Intel® Arria® 10 Devices
  • Do not drive the MSEL pins with a microprocessor or another device.
  • Use PS or FPP MSEL pin setting for configuration via HPS.
Configuration Scheme VCCPGM (V) Power-On Reset (POR) Delay Valid MSEL[2..0]
JTAG-based configuration Use any valid MSEL pin settings below
AS (x1 and x4) 1.8 Fast 010
Standard 011

PS and

FPP (x8, x16, and x32)

1.2/1.5/1.8 Fast 000
Standard 001

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