1. CvP Initialization in Intel® Arria® 10 2. Design Considerations for CvP Initialization in Intel® Arria® 10 3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10 4. CvP Driver and Registers 5. Partial Reconfiguration over PCI Express in Intel® Arria® 10 6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10 7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register 4.3.2. Altera-defined Vendor Specific Header Register 4.3.3. Altera Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
3.5. Bringing up the Hardware
Before testing the design in hardware, you must install Jungo WinDriver or CvP driver in your DUT system. You can also install RW Utilities or other system verification tools to monitor the link status of the Endpoint and to observe traffic on the link. You can download these utilities for free from many web sites.
Note: Intel® does not provide Jungo WinDriver as a part of Intel® Quartus® Prime install package starting with software version 19.1. You can develop your own custom CvP driver for Linux using the sample Linux driver source code provided by Intel® .
Note: The Linux driver provided by Intel® is not a production driver. You must adapt this driver to your design's strategy.
The test setup includes the following components:
- Intel® Arria® 10 FPGA Development Kit
- USB Blaster
- A DUT PC with PCI Express slot to plug in the Intel® Arria® 10 FPGA Development Kit
- A host PC running the Quartus Prime software to program the periphery image, .sof or .jic file
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