Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

1.2. CvP System

The following figure shows the required components for a CvP system.

Figure 1. CvP Block Diagram

A CvP system typically consists of an FPGA, a PCIe host, and a configuration device.

  1. The configuration device is connected to the FPGA using the conventional configuration interface. The configuration interface can be any of the supported schemes, such as active serial (AS), passive serial (PS), or fast passive parallel (FPP). The choice of the configuration device depends on your chosen configuration scheme.
  2. PCIe Hard IP block (bottom left) for CvP and other PCIe applications.
  3. PCIe Hard IP block only for PCIe applications and cannot be used for CvP.

Most Intel® Arria® 10 FPGAs include more than one Hard IP block for PCI Express. The CvP configuration scheme can only utilize the bottom left PCIe Hard IP block on each device. It must be configured as an Endpoint.