Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

5.2. PR over PCIe System

This is a generic design organization for any PR over PCIe design.
Figure 11. Block Diagram of PR over PCIe AVMM Design

As shown in the diagram, a PCIe card with Altera FPGA plugged in a host PC. The host PC sends the PR bit-stream to the Hard IP for PCIe in the form of packets using the application software. The packets are then received by the PR IP core through Avalon MM slave interface. The PR IP core acts as the master to the hard PR control block. It controls the flow of control and data bits to the PR control block as well as sends back the status from the PR control block to the host PC through the PCIe endpoint.