Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

3.1. Generating the Synthesis HDL Files for Intel® Arria® 10 PCI Express IP Core

Follow these steps to generate the synthesis HDL files with CvP enabled:.

  1. On the Tools menu, select Platform Designer .
  2. Open .qsys file of the project.
  3. On the System Contents tab, right-click Intel® Arria® 10 Hard IP for PCI Express and select Edit.
  4. Under System Settings, turn on Enable Configuration via Protocol as shown in the following figure:
    Figure 5. Illustrating the specified option in Systems Setting dialog box
  5. Click Finish.
  6. On the Generation tab, specify your parameters to generate RTL. Then click Generate at the bottom of the window.

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