Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
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4.3.6. CvP Data Registers

Table 12.  CvP Data Register (Byte Offsets: 0x224 - 0x228)
Bits Name Reset Value Access Description
[31:0] CVP_DATA2 0x00000000 RW Contains the upper 32 bits of a 64-bit configuration data. Software must ensure that all Bytes in both dwords are enabled. Use of 64-bit configuration data is optional.
[31:0] CVP_DATA 0x00000000 RW Write the configuration data to this register. The data is transferred to the FPGA control block to configure the device.

Every write to this register sets the data output to the FPGA control block and generates <n> clock cycles to the FPGA control block as specified by the CVP_NUM_CLKS field in the CvP Mode Control register. Software must ensure that all bytes in the memory write dword are enabled.

You can access this register using configuration writes. Alternatively, when in CvP mode, this register can also be written by a memory write to any address defined by a memory space BAR for this device. Using memory writes are higher throughput than configuration writes.