Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

5.3. Partial Reconfiguration Design Flow

The PR design flow requires initial planning. This planning involves setting up one or more design partitions, and then determining the placement assignments in the floorplan. Well-planned PR partitions improve design area utilization and performance. The Intel® Quartus® Prime software also allows you to create nested PR regions as part of an HPR flow. Reprogramming a child PR region does not affect the parent or the static region. In the HPR flow, reprogramming the parent region, reprograms the associated child region with the default child persona, without affecting the static region. The HPR flow does not impose any restrictions on the number of sub-partitions you can create in your design.

The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

Figure 12. Partial Reconfiguration Design Flow

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