1.4. CvP Initialization
In CvP, you partition your design into two images: core image and periphery image.
- Periphery image (*.periph.jic) — contains general purpose I/Os (GPIOs), I/O registers, the GCLK, QCLK, and RCLK clock networks, and logic that is implemented in hard IP such as the JTAG interface, PR block, CRC block, Oscillator block, Impedance control block, Chip ID, ASMI block, Remote update block, Temperature sensor, and Hard IP for PCI Express IP Core. These components are included in the periphery image because they are controlled by I/O periphery register bits. The entire periphery image is static and cannot be reconfigured.
- Core image (*.core.rbf) — contains logic that is programmed by configuration RAM (CRAM). This image includes LABs, DSP, and embedded memory. The single static core image may include PR reconfigurable regions.
- Reconfigurable region — This region can be programmed in user mode while the PCIe link is up and fully enumerated. It must contain only resources that are controlled by CRAM such as LABs, embedded RAM blocks, and DSP blocks in the FPGA core image. It cannot contain any periphery components such as GPIOs, transceivers, PLL, I/O blocks, the Hard IP for PCI Express IP Core, or other components included in the periphery image.
- Static region — This region cannot be modified.
The periphery image is stored in an external configuration device and is loaded into the FPGA through the conventional configuration scheme. The core image is stored in a host memory and loaded into the FPGA through the PCIe link. All other periphery and core resources are frozen until the FPGA enters user mode.
After the periphery image configuration is complete, the CONF_DONE signal goes high and allows the FPGA to start PCIe link training. During PCIe link training, the FPGA is not in user mode. When PCIe link training is complete, the PCIe link transitions to L0 state and then through PCIe enumeration. The PCIe host then initiates the core image configuration through the PCIe link.
After the core image configuration is complete, the CvP_CONFDONE pin goes high, indicating the FPGA is fully configured.
After the FPGA is fully configured, the FPGA enters user mode. If the INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is complete and the FPGA enters user mode.
In user mode, the PCIe links are available for normal PCIe applications. You can also use PR over PCI Express to change re-configurable regions within the single CvP core image.