Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express User Guide

ID 683871
Date 9/01/2020
Document Table of Contents

6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10

Partial reconfiguration is based on the use of revisions in the Quartus Prime Pro edition software. Your initial design is the base revision, where you define the boundaries of the static region and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions, which contain the static region and describe the differences in the reconfigurable regions.

The PR design flow requires more initial planning than a standard design flow. Planning requires setting up the design logic for partitioning, and determining placement assignments to create a floorplan. You should have well-planned partitions to improve the design area utilization and performance, and make timing closure easier.

Refer to the following application notes that provides a comprehensive walkthrough using the dedicated reference designs: You can extend these reference designs to meet your requirements, then run your custom design on the fully functional system that enables communication over PCIe.