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1. CvP Initialization in Intel® Arria® 10
2. Design Considerations for CvP Initialization in Intel® Arria® 10
3. Understanding the Design Steps for CvP Initialization in Intel® Arria® 10
4. CvP Driver and Registers
5. Partial Reconfiguration over PCI Express in Intel® Arria® 10
6. Understanding Design Steps for PR over PCI Express in Intel® Arria® 10
7. Document Revision History for the Intel® Arria® 10 CvP Initialization and Partial Reconfiguration over PCI Express* User Guide
4.3.1. Altera-defined Vendor Specific Capability Header Register
4.3.2. Altera-defined Vendor Specific Header Register
4.3.3. Altera Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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4.3.9. Uncorrectable Internal Error Mask Register
This register controls which errors are forwarded as internal uncorrectable errors. With the exception of the configuration errors detected in CvP mode, all of the errors are severe and may place the device or PCIe link in an inconsistent state. The configuration error detected in CvP mode may be correctable depending on the design of the programming software.
Bits | Reset Value | Access | Description |
---|---|---|---|
[31:12] | 0x00 | RO | Reserved. |
[11] | 1'b1 | RWS | Mask for RX buffer posted and completion overflow error. |
[10] | 1'b1 | RWS | Mask for parity error on the R2CSEB interface. |
[9] | 1'b1 | RWS | Mask for parity error on the Configuration Space to TX bus interface. |
[8] | 1'b1 | RWS | Mask for parity error on the TX to Configuration Space bus interface. |
[7] | 1'b1 | RWS | Mask for parity error in the transaction layer packet. |
[6] | 1'b1 | RWS | Mask for parity error in the application layer. |
[5] | 1'b0 | RWS | Mask for configuration error in CvP mode. |
[4] | 1'b1 | RWS | Mask for data parity errors detected during TX Data Link LCRC generation. |
[3] | 1'b1 | RWS | Mask for data parity errors detected on the RX to Configuration Space Bus interface. |
[2] | 1'b1 | RWS | Mask for data parity error detected at the input to the RX Buffer. |
[1] | 1'b1 | RWS | Mask for the retry buffer uncorrectable ECC error. |
[0] | 1'b1 | RWS | Mask for the RX buffer uncorrectable ECC error. |