Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

2.1.1. Power-On Reset (POR)

Ensure you power each of the power rails according to the power sequencing consideration until they reach the required voltage levels. In addition, the power-up sequence must meet either the standard or the fast power-on reset (POR) delay time.

Did you find the information on this page useful?

Characters remaining:

Feedback Message