3.1.3. First-Stage Bootloader
In HPS first boot mode, phase 1 configuration is successful as long as HPS OSC and HPS EMIF clocks are running stable.
For a generic transceiver use case, if the XCVR ref clock is not running during phase 2 configuration, the phase 2 configuration still succeeds.
For a PCIe use case, if the PCIe ref clock is not running during phase 2 configuration, the configuration fails.
You can create the FSBL from one of the following sources:
- U-Boot secondary program loader (SPL)
- Intel® provides the source code for U-Boot on GitHub.
- Arm* Trusted Firmware
- Intel provides the source code for the Arm* Trusted Firmware on GitHub.
The latest source code is also available on the Intel public git repository.
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