Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

4.5.1. FPGA Configuration First

The following figure shows an overview of the process:
Figure 12. Configuration over JTAG with FPGA Configuration First

The following steps are involved:

  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file or use a precompiled HPS FSBL hex file.
  3. Add the HPS FSBL hex file to the SOF file to obtain the HPS SOF File. SOF files resulted from compiling hardware designs that have HPS instantiated cannot be used directly to configure the device.
  4. Use the Intel® Quartus® Prime Programmer to configure the device over JTAG with the resulted HPS SOF file. The required firmware to run on the SDM must be downloaded on the device by the Intel® Quartus® Prime Programmer.
Run the following command to add the HPS FSBL hex file to the SOF file to create the HPS SOF file:
quartus_pfg -c design.sof design_hps.sof -o hps_path=fsbl.hex
The input and output files for this command are:
  • Input Files:
    • design.sof
    • fsbl.hex
  • Output File:
    • design_hps.sof

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