1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
6. Configuring the FPGA Fabric from HPS Software
Configuring the FPGA fabric from HPS software is supported only when using the HPS Boot First mode.
When creating the configuration files, you obtain a phase 1 HPS configuration file, and a phase 2 FPGA fabric configuration file. Typically, the two files come from running the Intel® Quartus® Prime Programming File Generator on a SOF file resulted from compiling a hardware project.
The phase 1 and phase 2 configuration files can also be obtained from different projects, or modified projects, if the following conditions are met:
- The same Programming File Generator version is used for generating both files, as this ensures both have the same SDM firmware version.
- Both SOF files that are used have the same HPS IO settings and HPS DDR settings.
- The FPGA fabric can be configured from both U-Boot and Linux.
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