Intel® Stratix® 10 SoC FPGA Boot User Guide

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ID 683847
Date 1/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
1. Introduction x
1.1. Glossary 1.2. Intel® Stratix® 10 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration - First Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 2.1.63.1.6. Application2.1.63.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.2. Intel® Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
5. Golden System Reference Design and Design Examples x
5.1. Golden System Reference Design 5.2. Bootloader Examples 5.3. Additional Design Examples
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux 6.3. FPGA Partial Reconfiguration from Linux
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* DS* Intel® SoC FPGA Edition 7.3. Other Debug Considerations
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. Golden System Reference Design and Design Examples
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow
8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives
9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide

4.5.2. HPS Boots First

In order to obtain the SOF file to be used to configure the device through JTAG with the HPS Boots First option, you need to generate a bitstream intended for another configuration method, such as AVST. An SOF file called design_hps_auto.sof is expected to be created automatically, and it can be used to configure the device. You discard or ignore the Phase 1 AVST bitstream, and use the Phase 2 bitstream to later configure the FPGA fabric from HPS software.

The following figure shows an overview of the process:
Figure 13. Configuration over JTAG with HPS Boots First
The following steps are involved:
  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
  3. Use Programming File Generator to create the following files:
    • Raw Binary File (RBF): contains the small phase 1 configuration bitstream. Discard this file.
    • hps_auto SOF File: contains the phase 1 configuration data, and the HPS FSBL.
    • Core RBF File: contains the typically much larger phase 2 configuration bitstream. To be used by HPS software later to configure the fabric.
  4. Use Intel® Quartus® Prime Programmer to configure the device using the phase 1 hps_auto SOF file. HPS software starts running, beginning with HPS FSBL.
  5. At a later time, HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
The following example creates the files for HPS boot first: 
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on
The input and output files for this command are:
  • Input Files:
    • design.sof
    • fsbl.hex
  • Output Files:
    • design.hps.rbf—to be discarded
    • design_hps.auto.sof—Phase 1 SOF
    • design.core.rbf—Phase 2 Core RBF
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