Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/17/2024
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4.5.2. HPS Boots First

In order to configure a device over JTAG with HPS first, you need to generate a bitstream intended for AVST. Two RBF files are created: design.hps.rbf Phase 1 bitstream which is used for initial device configuration over JTAG, and design.core.rbf Phase 2 bitstream used for later fabric configuration by HPS software.

The following figure shows an overview of the process:
Figure 13. Configuration over JTAG with HPS Boots First
The following steps are involved:
  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
  3. Use Programming File Generator to create the following files:
    • Peripheral RBF file—contains the phase 1 configuration bitstream for initial configuration over JTAG.
    • Core RBF file—contains the phase 2 configuration bitstream. To be used by HPS software later to configure the fabric.
  4. Use Intel® Quartus® Prime Programmer to configure the device using the phase 1 peripheral RBF. HPS software starts running, beginning with HPS FSBL.
  5. At a later time, HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
The following example creates the files for HPS boot first:
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on
The input and output files for this command are:
  • Input Files:
    • design.sof
    • fsbl.hex
  • Output Files:
    • design.hps.rbf—Phase 1 Peripheral RBF
    • design.core.rbf—Phase 2 Core RBF