Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

4.5.2. HPS Boots First

In order to obtain the SOF file to be used to configure the device through JTAG with the HPS Boots First option, you need to generate a bitstream intended for another configuration method, such as AVST. An SOF file called design_hps_auto.sof is expected to be created automatically, and it can be used to configure the device. You discard or ignore the Phase 1 AVST bitstream, and use the Phase 2 bitstream to later configure the FPGA fabric from HPS software.

The following figure shows an overview of the process:
Figure 13. Configuration over JTAG with HPS Boots First
The following steps are involved:
  1. Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
  2. Compile the HPS FSBL source code to obtain the HPS FSBL hex file, or use a precompiled one.
  3. Use Programming File Generator to create the following files:
    • Raw Binary File (RBF): contains the small phase 1 configuration bitstream. Discard this file.
    • hps_auto SOF File: contains the phase 1 configuration data, and the HPS FSBL.
    • Core RBF File: contains the typically much larger phase 2 configuration bitstream. To be used by HPS software later to configure the fabric.
  4. Use Intel® Quartus® Prime Programmer to configure the device using the phase 1 hps_auto SOF file. HPS software starts running, beginning with HPS FSBL.
  5. At a later time, HPS software configures the FPGA fabric by using the phase 2 Core RBF bitstream.
The following example creates the files for HPS boot first:
quartus_pfg -c design.sof design.rbf -o hps_path=fsbl.hex -o hps=on
The input and output files for this command are:
  • Input Files:
    • design.sof
    • fsbl.hex
  • Output Files:
    • design.hps.rbf—to be discarded
    •—Phase 1 SOF
    • design.core.rbf—Phase 2 Core RBF

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