4.4. Programming File Generator
The tool that is used for creating the configuration files is called Programming File Generator. This tool is part of the Intel® Quartus® Prime Programmer, which is included with the full Intel® Quartus® Prime software installation. The Intel® Quartus® Prime Programmer can also be downloaded and installed separately as a standalone application, in which case less disk space would be required.
- Adding an HPS FSBL hex file to a SOF file is only supported by the command line version.
- Creating the initial flash contents for a Remote System Update (RSU) system is only supported by the graphical interface version.
The command line version is typically more convenient to use, as it requires less parameters to be entered than the graphical interface version. The graphical interface version also has the capability of saving all the selected options in a .pfg file, by going to File > Save or File > Save As menus. The saved .pfg file can later be used to re-create the configuration files by running the quartus_pfg -c filename.pfg command. The .pfg file is an XML file, typically not editable by hand. One useful edit though is to replace absolute filenames with relative ones, so that the tool could be ran in a different folder than the one where the .pfg file was originally created.
The following table summarizes the file types handled by the Intel® Quartus® Prime Programming File Generator:
|File Extension||File Type||Description|
|.jic||JTAG Indirect Configuration File||These files are intended to be written to QSPI flash by using the Intel® Quartus® Prime Programmer tool. They contain the actual flash data, and also a flash loader, which is a small FPGA design used by the Intel® Quartus® Prime Programmer to write the data.|
|.rpd||Raw Programming Data File||These files contain actual binary content for the flash and no additional metadata. They can contain the full content of the flash, similar with the .jic file—this is typically used in the case where an external tool is used to program the initial flash image. They can also contain an RSU application image, or RSU factory update image.|
|.rbf||Raw Binary File||
These files are binary files which can be used typically to configure the FPGA fabric for HPS configuration first mode. They can also be used for passively configuring the FPGA device through Avalon® Streaming Interface. They are also used for configuring the FPGA fabric for CvP case.
The maximum size of the .core.rbf file for the FPGA core fabric from the HPS does not exceed the bit-stream size for the FPGA from a configuration device.
The maximum size of bit-stream can be found in the Configuration Bit Stream Sizes section in the Intel® Stratix® 10 Device Data Sheet .
|.map||Memory Map File||These files contain details about where the input data was placed in the output file. This file is human readable.|
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