Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

2.1.4. Second-Stage Bootloader

The second-stage bootloader (SSBL) is the second boot stage for the HPS. The FSBL initiates the copy of the SSBL to the HPS SDRAM. The SSBL typically enables more advanced peripherals such as Ethernet and supports command line interface.

You can create the SSBL from one of the following sources:
  • U-Boot
    • Intel provides the source code for U-Boot on GitHub.
  • UEFI
    • Intel provides the source code for UEFI on GitHub.
  • RTOS
  • Bare Metal application

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