Intel® Stratix® 10 SoC FPGA Boot User Guide

ID 683847
Date 1/20/2023
Document Table of Contents

3.1. Boot Flow Overview

You can boot the HPS and HPS EMIF I/O first before configuring the FPGA core and periphery. The MSEL[2:0] settings determine the source for booting the HPS. In this mode, any of the I/O allocated to the FPGA remain tri-stated while the HPS is booting. The HPS can subsequently request the SDM to configure the FPGA core and periphery, excluding the HPS EMIF I/O. Software determines the configuration source for the FPGA core and periphery. In HPS First Boot mode, you have the option of configuring the FPGA core during the SSBL stage or after the operating system boots.

Note: Configuring the HPS EMIF I/O for the first time and then loading the HPS FSBL is called "Phase 1 configuration". The subsequent configuration of FPGA core and periphery by HPS is called "Phase 2 configuration". The phase 1 and phase 2 configuration files must be generated from the same Intel® Quartus® Prime Pro Edition software version, this includes patches installed if applicable.

A typical HPS First Boot flow may look like the following figure. You can use U-Boot, Unified Extensible Firmware Interface (UEFI), or a custom bootloader for your FSBL or SSBL. An example of an OS is Linux or an RTOS. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).

Figure 6. Typical HPS Boot First Flow
Table 5.  HPS Boot First Stages
Time Boot Stage Device State
TPOR POR Power-on reset
T1 to T2 SDM- Boot ROM
  1. SDM samples the MSEL pins to determine the configuration and boot source. It also establishes the device security level based on eFuse values.
  2. SDM firmware initializes the device.
  3. SDM authenticates and decrypts the bitstream (this process occurs as necessary throughout the configuration).
T2 to T3 SDM- Configuration Firmware
  1. SDM configures the HPS EMIF I/O and the rest of the user-configured SDM I/O.
  2. SDM loads the FSBL from the bitstream into HPS on-chip RAM.
  3. SDM enables HPS SDRAM I/O and optionally enables HPS debug.
  4. HPS is released from reset.
T3 to T4 First Stage Bootloader (FSBL)
  1. The FSBL initializes the HPS, including the SDRAM.
  2. FSBL obtains the SSBL from HPS flash or by requesting flash access from the SDM.
  3. FSBL loads the SSBL into SDRAM.
  4. HPS peripheral I/O pin multiplexer and buffers are configured. Clocks, resets and bridges are also configured.
  5. HPS I/O peripherals are available.
  6. HPS bootstrap completes.
T4 to T5 Second Stage Bootloader (SSBL)

After bootstrap completes, any of the following steps may occur:

  1. The FPGA core configuration loads into SDRAM from one of the following sources:
    • SDM flash
    • HPS alternate flash
    • EMAC interface
  2. HPS requests that the SDM configure the FPGA core.2
  3. FPGA enters user mode.
  4. OS is loaded into SDRAM.
T5 to TBoot_Complete Operating System (OS)
  1. OS boot occurs and the OS schedules applications for runtime launch.
  2. (Optional step)The OS initiates FPGA configuration through a secure monitor call (SMC) to the resident SMC handler (typically SSBL), which then initiates the request to the SDM.
Note: The location of the source files for configuration, FSBL, SSBL and OS can vary. For more information, refer to the System Layout for HPS Boot First Mode section.
Note: To avoid configuration failures, the Intel® Stratix® 10 device requires clocks for the PCIe* and all E-tile transceiver reference clocks. You must provide the input reference clock, refclk, and it must be free-running and stable at device power up for a successful device configuration.
L- and H-tile (does not apply to E-tile) —the refclk requirement is mandatory if you are configuring your Intel® Stratix® 10 device over a PCIe* link; otherwise the refclk requirement is not mandatory for a non PCIe* use case.
  • For PCIe* use case, the firmware waits for the PLL calibration code to ensure the PLL is calibrated properly in order to release the device for entering into user mode. Therefore, refclk is mandatory for PLL calibration.
  • For non PCIe* use case, without refclk supply during configuration, the firmware does not gate device configuration without a proper PLL calibration code. You can calibrate the XCVR PLL in user mode for XCVR channels to operate properly.
E-tile (does not apply to L- and H-tile )—the refclk requirement is mandatory. E-tile does not support the PCIe* use case.
  • The E-tile refclk is needed to load the firmware (from the FPGA configuration bit stream) into the E-Tile.
2 FPGA I/O and FPGA core configuration can occur at the SSBL or OS stage, but is typically configured during the SSBL stage.

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