3.1. Boot Flow Overview
You can boot the HPS and HPS EMIF I/O first before configuring the FPGA core and periphery. The MSEL[2:0] settings determine the source for booting the HPS. In this mode, any of the I/O allocated to the FPGA remain tri-stated while the HPS is booting. The HPS can subsequently request the SDM to configure the FPGA core and periphery, excluding the HPS EMIF I/O. Software determines the configuration source for the FPGA core and periphery. In HPS First Boot mode, you have the option of configuring the FPGA core during the SSBL stage or after the operating system boots.
A typical HPS First Boot flow may look like the following figure. You can use U-Boot, Unified Extensible Firmware Interface (UEFI), or a custom bootloader for your FSBL or SSBL. An example of an OS is Linux or an RTOS. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).
|Time||Boot Stage||Device State|
|T1 to T2||SDM- Boot ROM||
|T2 to T3||SDM- Configuration Firmware||
|T3 to T4||First Stage Bootloader (FSBL)||
|T4 to T5||Second Stage Bootloader (SSBL)||
After bootstrap completes, any of the following steps may occur:
|T5 to TBoot_Complete||Operating System (OS)||
- For PCIe* use case, the firmware waits for the PLL calibration code to ensure the PLL is calibrated properly in order to release the device for entering into user mode. Therefore, refclk is mandatory for PLL calibration.
- For non PCIe* use case, without refclk supply during configuration, the firmware does not gate device configuration without a proper PLL calibration code. You can calibrate the XCVR PLL in user mode for XCVR channels to operate properly.
- The E-tile refclk is needed to load the firmware (from the FPGA configuration bit stream) into the E-Tile.
Power-On Reset (POR)
Secure Device Manager
Did you find the information on this page useful?