1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
2.2.3. Single SDM Flash
In this case, the Quad SPI flash connected to the SDM contains all the data required for configuring and booting the system, including the configuration bitstream, bootloader and OS files.
Note: When you use the HPS to access the SDM Quad SPI, it operates at a lower bandwidth of ~4-6 MB/s. This is due to the high latency of the PSI link between HPS and SDM, and the fact that all transfers are done in Programmed IO (PIO) mode, instead of DMA mode.
Software running on the HPS must request permission from the SDM to get exclusive access to the QSPI before using it. This is already implemented in the U-Boot and UEFI bootloaders supported by Intel® .
Figure 4. FPGA Configuration First Layout with Quad SPI
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