1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
4.6.2. FPGA Configuration First
The following figure shows an overview of configuring from QSPI when using FPGA configuration first:
Figure 14. Configuration from QSPI using FPGA Configuration First
The following steps are involved:
- Compile hardware project with Intel® Quartus® Prime to obtain the SOF file.
- Compile the HPS FSBL source code to obtain the HPS FSBL hex file or use a precompiled one.
- Use Programming File Generator to create the following files:
- JTAG Indirect Configuration (JIC) File: contains the configuration bitstream to be written to flash and SDM helper image used by the Intel® Quartus® Prime Programmer to write the bitstream to flash.
- [Optional] Raw Programming Data (RPD) File: contains the configuration bitstream in plain binary format. Can be written to flash with a 3rd party programmer, such as U-Boot.
- [Optional] Map File: describes the actual flash usage in human-readable text format.
- Use the Intel® Quartus® Prime Programmer to write the JIC image to QSPI flash. Alternatively, use a 3rd party programmer to write the RPD image to flash.
- Set MSEL to QSPI, then power up, power cycle or toggle nCONFIG to cause the device to configure itself from QSPI.
- FPGA device is configured, and after INIT_DONE the HPS FSBL is also executed.
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