1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
2.1. Boot Flow Overview for FPGA Configuration First Mode
You can program the Intel Stratix 10 SoC device to configure the FPGA first and then boot the HPS. The available configuration data sources configure the FPGA core and periphery first in this mode. After completion, you may optionally boot the HPS. All of the I/O, including the HPS-allocated I/O, are configured and brought out of tri-state. If the HPS is not booted:
- The HPS is held in reset.
- HPS-dedicated I/O are held in reset.
- HPS-allocated I/O are driven with reset values from the HPS.
If the FPGA is configured before the HPS boots, the boot flow looks like the example figure below. The flow includes the time from power-on-reset (TPOR) to boot completion (TBoot_Complete).
Figure 1. Typical FPGA Configuration First Boot Flow
|Time||Boot Stage||Device State|
|TPOR to T1||POR||Power-on reset|
|T1 to T2||Secure Device Manager (SDM)- Boot ROM||
|T2 to T3||SDM- configuration firmware||
|T3 to T4||First-Stage Bootloader (FSBL)||
|T4 to T5||Second-Stage Bootloader (SSBL)||
|T5 to TBoot_Complete||Operating System (OS)||The OS boots and applications are scheduled for runtime launch.|
Note: The location of the source files for configuration, FSBL, SSBL, and OS can vary and are described in the System Layout for FPGA Configuration First Mode section.
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