1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
188.8.131.52. Creating Configuration Files from Command Line
The following example command creates the QSPI configuration files for FPGA configuration first mode:
quartus_pfg -c design.sof design.jic design.rpd design.map \ -o hps_path=fsbl.hex \ -o device=MT25QU128 \ -o flash_loader=1SX280LU2 \ -o mode=ASX4 \ -o bitswap=on
The input and output files for this command are:
- Input Files:
- Output Files:
The command parameters are listed below:
|hps_path||Location of HPS FSBL file in hex format|
|device||Target QSPI device. Use a device listed in Supported QSPI Devices or use the graphical interface to determine available options.|
|flash_loader||Which helper image to be used for writing JIC to flash. It is typically a prefix of your FPGA part number. Use the graphical interface mode to determine available options.|
|mode||ASX4 for QSPI|
|bitswap||Set to "on" to create RPD with plain binary format, usable by 3rd party tools.|
Note: If your design is small, you can target a QSPI device that is smaller than what you have on board. When programming the resulted JIC file, a warning is displayed, but the resulted file size and erasing and programming times are reduced accordingly.
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