1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. Golden System Reference Design and Design Examples 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Intel® Stratix® 10 SoC FPGA Boot Flow 8. Intel® Stratix® 10 SoC FPGA Boot User Guide Archives 9. Document Revision History for Intel® Stratix® 10 SoC FPGA Boot User Guide
4.1. Overview 4.2. Intel® Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration
5.1. Golden System Reference Design
The Golden System Reference Design (GSRD) is a thoroughly tested known good design showcasing a system using both HPS and FPGA resources, intended to be used as a baseline project.
The GSRD is comprised of the following components:
- Golden Hardware Reference Design (GHRD)
- Reference HPS software including:
- Arm Trusted Firmware
- Linux Kernel
- Linux drivers
- Sample applications
The current GSRD uses HPS First configuration mode, with U-Boot configuring the FPGA fabric.
The full documentation for the GSRD includes details on both how to use the pre-built binaries and also how to rebuild them if needed. The GSRD includes a complete PR example, including recipes to build the PR binaries and instructions used to exercise different PR scenarios from Linux.
The documentation can be referenced at the following link: Intel® Stratix® 10 SoC GSRD .
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